The electrical characteristics of some loads are such that, when these loads are connected to an electrical power source, the loads may initially draw relatively large electrical currents. This relatively large initial electrical current draw is generally referred to as inrush current. If the inrush current is excessive, circuit elements can be damaged. Thus, for loads that draw relatively large inrush current, an inrush current suppression circuit may be placed between the electrical power source and the load. An inrush current suppression circuit, as its name implies, suppresses the inrush current for a relatively short time, after which the load is enabled to be fully energized.
In some implementations, enablement of the load to be fully energized is based on one or more timers. That is, full enablement of the load is delayed until the one or more timers time-out. While this technique, as well as various others, is generally effective, it can exhibit certain drawbacks in relatively high-precision circuits and systems. This is because the tolerance stack-ups of the timers and various other circuit components can lead to enablement of the load before inrush current limiting is complete, which can in turn lead to faults and component damage. Moreover, sensing voltage across the inrush current suppression circuit can be inadequate because the load is disabled during the inrush limiting cycle. The load being disabled, plus the addition of power line noise, leads to a low voltage drop, which can result in false enabling of the load.
Hence, there is a need for a circuit and method that limits inrush current for a sufficient period of time before full-enablement of a load, and which does not exhibit undesirable component stack-ups. The present invention addresses at least this need.